At present, the planning of standards is proceeding as the IEEE 802.15 group of standards in relation to WPAN. With regard to network topology and media-access protocols, specifications have already been decided in the IEEE 802.15.3 standard. Furthermore, MBOA specifications and DS-UWB specifications, etc., based on UWB (Ultra-Wide Band) communication schemes have been proposed as high-speed WPAN standards.
FIG. 3 is a diagram illustrating the structure of a wireless frame in a WPAN system proposed in specifications.
As illustrated, the WPAN wireless frame is composed of a header 300 and data payload 301. The header 300 contains information necessary for protocol processing in the PHY or MAC layer. User data is transported by the data payload 301. The header 300 and data payload 301 include checksums, which are referred to as header check sequence (HCS) and frame check sequence (FCS), respectively, for the purpose of error detection or error correction.
FIG. 4 is a diagram useful in describing in further detail the header 300 included in the wireless frame of the WPAN system proposed in MBOA specifications.
The header 300 includes a PHY header 400 that holds the frame length of the wireless data frame, the data transfer rate and other wireless frame information as the PHY layer, and a MAC header 401 that holds a terminal identifier related to the MAC protocol. Furthermore, placed between the PHY header 400 and the MAC header 401 is a tail bit 402 in order to return a convolutional encoder in the transmitter and a Viterbi decoder in the receiver to their initial states. Further, an HCS 403 is appended to the end of the frame as a checksum for detecting or correcting an error that has occurred in the PHY header 400 or MAC header 401. The checksum used here is a CRC (Cyclic Redundancy Check) code based upon the generating polynomial G(X)=X16+X12+X5+1. Bit error that has occurred in the header 300 can be detected or corrected using the code characteristic of the HCS.
With the basic method of error detection and error correction based upon this CRC code, first division based upon the generating polynomial G(X) is performed over the entirety of the message portion and checksum, and then the remainder is found. In the case of a 16-bit CRC code, for example, the remainder is a 16-bit value and generally is referred to as a “syndrome”. If the syndrome is “0”, then it is guaranteed that the message and checksum are entirely free of error. If the syndrome is not “0”, on the other hand, detection or correction of the error that has occurred can be performed using a syndrome value that is non-zero (≠0) but the number of error bits capable of being detected or corrected is dependent upon the code characteristic of the CRC code used. It is known that the polynomial G(X) used here makes possible 1-bit error correction and error detection of up to three bits.
Japanese Patent Laid-Open No. 2001-186108 can be mentioned as a conventional example of an error detection or error correction method using a CRC code. In Japanese Patent Laid-Open No. 2001-186108, rather than calculating a syndrome directly with respect to a received sequence and applying an error correction based upon this value in the manner described above, maximum-likelihood decoding, in which it is assumed that an error has occurred at each bit position in the receive data sequence, is performed. More specifically, a decoder is equipped with a plurality of bit-inverting circuits, the number of which is the same as that of the code block lengths of the receive data, and with the same number of CRC circuits. Each of the bit inverting circuits forcibly inverts the symbol at the corresponding bit position in the receive data sequence, the outputs of the bit-inverting circuits are subjected to syndrome computations by respective ones of the plurality of CRC circuits, and a path for which the result of computation is “0” is adopted as decoded data, whereby the speed of error-correction/error-detection processing is raised.
Furthermore, Japanese Patent Laid-Open No. 7-135508 can be mentioned as a conventional example of an error detection or error correction method using a CRC code. This relates to a cell synchronization scheme with a distributed sample scrambler used in cell-based ATM (Asynchronous Transfer Mode). This method subjects an ATM cell header to error correction using a CRC code contained in this header and simultaneously synchronizes the operation timing of a descrambler to the data payload. Similarly, in a WPAN communication scheme compliant with the MBOA specifications, a checksum based upon a CRC code is appended to the header and scrambling processing using a scrambler is applied to the latter half of the header and to the data payload. Accordingly, even in a conventional WPAN communication system compliant with the MBOA specifications, header error correction is implemented by using a codec having a configuration similar to that of the well-known art.
FIG. 5 is a block diagram useful in describing the structure of a transmit-side codec in a WPAN wireless communication system compliant with MBOA specifications, and FIGS. 6A to 6D are diagrams useful in describing output data at various portions of a transmit-side codec.
A codec is provided together with a modem processing unit in a processor of the PHY layer and applies channel encoding to transmit data that has been accepted from a MAC processor. The transmit-side codec first accepts a PHY parameter 11 relating to the PHY layer and, in a PHY header generator 101, generates a PHY header of the kind shown in FIG. 6A in accordance with the decided format. Next, the generated PHY header, a tail bit and a MAC header accepted from the MAC processor are concatenated in a header concatenating unit 102 in accordance with the decided format. FIG. 6B depicts the structure of data thus generated and output from the header concatenating unit 102.
An HCS is generated by an HCS generator 103. The HCS generator 103 calculates an HCS as a CRC code by the generating polynomial G(X)=X16+X12+X5+1 with regard to the PHY header, tail bit and MAC header and adds the calculated 16-bit HCS to the latter part of the MAC header, as illustrated in FIG. 6C.
Furthermore, the header and data payload are subjected to scrambling processing by a scrambler 104. The latter is implemented by an exclusive-OR operation between a pseudo-random sequence, which is generated by a polynomial X15+X14+1, and the header and data payload. What is noteworthy here is that the PHY header and tail bit among the constituent elements of the header are not subjected to scrambling processing and that only the portion from the MAC header onward is subjected to scrambling processing, as illustrated in FIG. 6D. Furthermore, with regard to the initial state of the scrambler compliant with MBOA specifications, one is selected from among four types on a per-wireless-frame basis, and the generated pseudo-random sequence also is selected from among four types. Such a pseudo-random sequence used in scrambling processing is referred to as a “scramble pattern”. In order to identify the scrambler initial value selected at this time, a 2-bit field (scrambler seed field) within the PHY header is assigned as a scramble index field. As a result, by referring to this field, the receiver is capable of applying an operation that is the reverse of scrambling, namely descrambling processing, to the receive data using an identical scramble pattern generated from an initial state identical with that on the transmit side. If descrambling is performed in the receiver using a scramble pattern different from that of the transmit side, receive data that is completely different from the transmit data will be reproduced. This means that it is essential that the scramble patterns used on the transmit and receive sides match each other. In accordance with the MBOA specifications, scramble pattern information is shared using the scramble index field in order to achieve agreement between the scramble patterns of the transmitter and receiver.
The scrambled header and data payload are subsequently convolutionally encoded by a convolutional encoder 105 at an encoding rate that corresponds to the prescribe data transfer rate. Furthermore, in order to maintain the error correction capability manifested by the convolutional code with respect to the occurrence of burst error, the encoded data is interleaved on the frequency axis by an interleaver 106. Modulated data 13 thus channel encoded by the codec on the transmit side is delivered to a modem (not shown) and subjected to OFDM modulation, after which the data is transmitted as a UWB radio signal from an antenna via a radio frequency circuit.
FIG. 7 is a diagram illustrating the structure of a conventional receive-side codec in a WPAN wireless communication system compliant with MBOA specifications.
The receive-side codec first accepts demodulated data 21 from a modem and, using a deinterleaver 204, performs data rearrangement as an operation that is the reverse of interleaving at the time of transmission. Next, in order to decode convolutional code, decoding is performed typically by a Viterbi-algorithm decoder (Viterbi decoder 205). The decoded data 22 thus obtained is descrambled with regard to the portion of the header from the MAC header onward and with regard to the data payload by a descrambler 201. According to the MBOA specifications, one of four types of scramble initial values is selected, as described above. The descrambler on the receive-side codec acquires the initial value of the scrambler being used in the receive frame from the scramble index field that has been assigned to the PHY header of the header, and executes descrambling by an exclusive-OR operation with respect to the pseudo-random sequence.
Next, the output of the descrambler 201 is sent to a syndrome arithmetic unit 202 in order that error correction based upon a CRC code will be performed. The syndrome arithmetic unit 202 performs division, which is based upon the above-mentioned generating polynomial, over the PHY header, tail bit, MAC header and HCS and calculates the remainder as a syndrome. If the syndrome value thus calculated is “0”, then it is guaranteed that the received frame header is entirely free of error. In a case where the syndrome value is not “0”, on the other hand, a correction is performed by an error correction unit 203, which is connected to the output side of the syndrome arithmetic unit 202, if there is an error of one bit. If an error exceeding a single bit exists, the wireless frame is discarded on the grounds that the number of errors is such that the errors cannot be corrected. Receive data 23 thus error corrected is sent to a MAC processor.
Thus, with a conventional codec, correction of bit error contained in a header is performed using a CRC code. However, in a case where a bit error has occurred in the scramble index field contained in the PHY header, even an error that is one bit at most, a conventional codec will cause the descrambler 201 to operate based upon an improper scramble pattern and, as a result, apparent error spreads over the entire header.
FIGS. 8A to 8D are diagrams for describing a case where error correction can be performed correctly using a CRC code employing the conventional codec.
FIG. 8A illustrates a header before scrambling and FIG. 8B the header after scrambling. As described above, only the portion of the header from the MAC header onward is subjected to scrambling processing. FIG. 8C illustrates the received header. Here, as indicated at 800, a bit error has occurred in part of the scrambled MAC header. FIG. 8D illustrates the descrambled header. Here the position 800 at which the bit error occurred is maintained as is.
In a case where an error has thus occurred in a bit other than the scramble index field contained in the PHY header, the receive data is descrambled correctly by a scramble pattern identical with the scramble pattern used at the time of transmission. As a result, there is no change in the number bits in which the error occurred or in the bit positions even in the descrambler output. Even in a case where an error has occurred in a field (the MAC header, etc.) that is to undergo scrambling processing, scrambling/descrambling processing is a linear operation, namely an exclusive-OR operation between the scramble pattern and a data sequence. The number of bit errors and positions, therefore, are maintained. In such case error detection/correction can be performed normally by the conventional codec.
FIGS. 9A to 9D are diagrams for describing a case where error correction cannot be performed correctly using a CRC code employing the conventional codec.
FIG. 9A illustrates a header before scrambling and FIG. 9B the header after scrambling. As described above, only the portion of the header from the MAC header onward is subjected to scrambling processing (shown as a shaded portion in FIG. 9B). FIG. 9C illustrates the received header. Here, as indicated at 900, a bit error has occurred in the scramble index field within the PHY header, which does not undergo scrambling. FIG. 9D illustrates the descrambled header. Here bit error has spread across the entire header owing to non-agreement with the scramble pattern.
If a bit error thus occurs in the scramble index field contained in the PHY header, the descrambler of the receive-side codec decides the scramble pattern, which is to be used in descrambling, by referring to the scramble index field in which the error is included. Consequently, the scramble pattern used in descrambling becomes a scramble pattern that is different from the pattern that was used by the scrambler at the time of transmission. Since improper descrambling processing is thus executed by a scramble pattern different from that used in scrambling processing at the time of transmission, apparent bit error is enlarged in the descrambler output.
The header that has thus undergone improper descrambling by the descrambler is no longer one that can be subjected to normal error correction in the syndrome arithmetic unit and error correction unit located downstream. As a result, even if bit error that has occurred in the scramble index field is a single bit that is within the error correction capability of a CRC code, error correction can no longer be performed correctly. Further, this may bring about erroneous decisions of other types and may lead to a rise in the rate at which wireless frames are lost.